The present invention relates to an arbitration circuit which adjusts operating timings for reading, writing and the like carried out on an asynchronous basis in a first-in first-out memory (hereinafter called “FIFO memory”) or the like.
Since a read operation and a write operation are performed asynchronously in a FIFO memory, an internal read transfer operation (operation of transferring data read from each memory cell to its corresponding register) and a write transfer operation (operation of transferring data written into a register to its corresponding memory cell) are also fully performed asynchronously. Since, however, the operations of effecting reading and writing on each memory cell cannot be carried out simultaneously, access to the memory cell is done with the timings for the read and write operations being shifted. A circuit for controlling the timing provided to access each memory cell, based on the order of priority is of an arbitration circuit.
FIG. 2 is a configuration diagram showing one example of a conventional arbitration circuit.
The arbitration circuit comprises an arbitration unit 10 for write transfer control, an arbitration unit 20 for read transfer control, and a delay unit 30 for giving a priority to a write transfer. Since the arbitration units 10 and 20 are similar in configuration, the arbitration unit 10 will now be explained specifically.
The arbitration unit 10 has an SR type flip-flop (hereinafter called “FF”) 11. A set terminal S of the FF 11 is supplied with a write request signal WRQ. An output terminal Q of the FF 11 is connected to one input side of a two-input negative AND gate (hereinafter called “NAND”) 12. A read set signal RS of the arbitration unit 20 is supplied to the other input side of the NAND 12 as a delay read set signal RSD with being delayed by the delay unit 30. The output of the NAND 12 is supplied to a filter 13 and supplied to the arbitration unit 20 as a write set signal WS.
When the output of the NAND 12 changes from a level “L” to a level “H”, the filter 13 outputs a signal of “L” immediately. When the output of the NAND 12 changes from “H” to “L”, the filter 13 delays it and outputs a signal of “H”. The filter 13 has inverters 13a, 13b and 13c of three stages connected in tandem. The output of the NAND 12 is supplied to the first-stage inverter 13a. The output side of the inverter 13b is connected to a ground potential GND via a capacitor 13d. An AND gate (hereinafter called “AND”) 13e ANDs the outputs of the inverters 13a and 13c and outputs the result of ANDing as a write control signal WT. Further, the write control signal WT is ANDed with a transfer end signal END by an AND 14 and the result of ANDing is supplied to a reset terminal R of the FF 11.
The arbitration unit 20 is similar in configuration to the arbitration unit 10 because the write request signal WRQ, the write set signal WS and the write control signal WT employed in the arbitration unit 10 are simply read as a read request signal RRQ, a read set signal RS and a read control signal RT respectively.
On the other hand, the delay unit 30 delays an inputted read set signal RS only for a predetermined time and outputs a delay read set signal RSD in which a pulse width of “L” is made short. The delay unit 30 has an inverter which is constituted of a P channel MOS transistor (hereinafter called “PMOS”) 31 and an N channel MOS transistor (hereinafter called “NMOS”) 32 and which inverts the read set signal RS and outputs it. A capacitor 33 used as a delay element is connected between a node N 30 corresponding to the output side of the inverter and the ground potential GND.
Further, an inverter constituted of a PMOS 34 and an NMOS 35 is connected to the node N 30, and a delay read set signal RSD is outputted from the inverter. Incidentally, the gate widths of the NMOS 32 and the PMOS 34 are set larger than those of the PMOS 31 and the NMOS 35 respectively, whereby a pulse width of “L” to be outputted is set short.
FIG. 3 is a signal waveform diagram showing operations of FIG. 2.
When write and read requests are not made, the FFs 11 and 12 are reset by a transfer end signal END given prior to the write and read requests. Signals S11 and S21 outputted from the FFs 11 and 12 are of “L”. Thus, a write set signal WS and a read set signal RS are both brought to “H”, and a write control signal WT and a read control signal RT are both brought to “L”.
Now, when a read request signal RRQ is brought to “H” by the occurrence of the read request, the FF 21 is set so that its signal S21 changes to “H”. Thus, the read set signal RS changes to “L” immediately. However, the read control signal RT is not brought to “H” immediately because of a delay made by a filter 23 but kept in a state of “L” for a while. If the write request is not produced during this period, then the read control signal RT is delayed by the filter 23 and thereafter changes to “H”.
On the other hand, the read set signal RS is supplied to the delay unit 30 where it is delayed by a predetermined time. Therefore, a delay read set signal RSD is held “H” during the delay time of the delay unit 30.
Assume now that the write request is produced and a write request signal WRQ is brought to “H” during the period in which the delay read set signal RSD is “H”, immediately after the occurrence of the read request. With the “H” of the write request signal WRQ, the FF 11 is set and its signal S11 changes to “H”. Since the delay read set signal RSD is of “H” at this point of time, the write set signal WS outputted from the NAND 12 changes to “L” immediately.
Since the write set signal WS is supplied to the NAND 22, the read set signal RS outputted from the NAND 22 is returned to “H”. The read control signal RT outputted from the filter 23 remains at “L” and its change is stopped.
The filter 13 of the arbitration unit 10 outputs a write control signal WT of “H” after the elapse of a predetermined delay time in response to the write set signal WS of “L”. Consequentially, a write transfer is started.
When the write transfer is completed, a transfer end signal END is given. Thus, the FF1 is reset so that its signal S11 is brought to “L” and the write set signal WS and the write control signal WT are respectively returned to “H” and “L”. Since the read control signal RT is of “L” at this time, the FF 21 remains set and its signal S21 is “H”.
With the returning of the write set signal WS to “H”, a read set signal RS outputted from the NAND 22 is brought to “L” again and supplied to the filter 23 and the delay unit 30. If no write request signal WRQ is supplied within a predetermined delay time of the delay unit 30, then a delay read set signal RSD is brought to “L” after the delay time. With the setting of the delay read set signal RSD to “L”, priority processing of a subsequent write request signal WRQ is stopped.
After the delay time of the filter 23, the read control signal RT is brought to “H”, so that a read transfer is started. Incidentally, when the read transfer is completed, a transfer end signal END is given, whereby the FF 21 is reset, thus returning to a first or initial state.
In the arbitration circuit, the set signal of other arbitration unit is stopped base on the set signals WS and RS of the arbitration units 10 and 20 thereby to control the timings for the two transfer requests. In the arbitration circuit of such a system, there is a fear that such an oscillation state that the set signals WS and RS take “L” and “H” repeatedly alternately according to the timings for the two request signals WRQ and RRQ, is reached. In the arbitration circuit, the filters 13 and 23 provided within the arbitration units 10 and 20, and the delay unit 30 provided between the arbitration units 10 and 20 suppress the oscillations of the set signals WS and RS. That is, the outputs (changes from “H” to “L”) of the set signals WS and RS are delayed by the filters 13 and 23 respectively, and the period during which the set signal RS is “L” is shortened by the delay unit 30, thereby attenuating such a pulse width that each of the set signals WS and RS becomes “L” to suppress the oscillations.
The above-related art refers to a patent document 1 (Japanese Unexamined Patent Publication No. 2004-348463).
In the arbitration circuit, however, there has arisen a feat that the pulse widths of the set signals WS and RS would become short extremely depending upon the timings for the read and write requests, thus resulting in a malfunction.
FIG. 4 is a signal waveform diagram for describing the problems of the arbitration circuit shown in FIG. 2.
When, as shown in FIG. 4, the timings provided to input the write request signal WRQ and the read request signal RRQ are away a little from each other and the set of the write set signal WS by the write request signal WRQ and the reset of the read set signal RS by the read request signal RRQ are close to each other, the time during which the write set signal WS is brought to “L”, becomes short. At this time, the time during which the read set signal RS is brought to “H” becomes short.
When the time during which the read set signal RS goes “H” becomes short, a change in the amplitude of a signal S30 of the node N30 in the delay unit 30 becomes small. When the change in the amplitude of the signal S30 becomes smaller, the pulse width of the read set signal RS corresponding to the input signal of the delay unit 30 and the pulse width of the delay read set signal RSD corresponding to its output signal remain almost unchanged.
Therefore, such a state that the output signal of the delay unit 30 is outputted from the delay unit 30 as the read set signal RSD and the input signal of the delay unit 30 is inputted to the delay circuit 30 as the read set signal RS again, is repeated almost without attenuation of the pulse width of the read set signal RS. Thus, a problem arose in that the set signals WS and RS would be in an oscillation state, thereby causing a malfunction.